• DocumentCode
    1883912
  • Title

    A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR

  • Author

    Wenbo Liu ; Pingli Huang ; Yun Chiu

  • Author_Institution
    Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
  • fYear
    2010
  • fDate
    7-11 Feb. 2010
  • Firstpage
    380
  • Lastpage
    381
  • Abstract
    A perturbation-based background digital calibration enables the capacitance scaling to the kT/C limit in a 12b SAR ADC. Combined with a dynamic threshold comparison technique, the 0.13¿m CMOS prototype measures a 71.1dB peak SNDR, a 94.6dB peak SFDR, and a peak FoM of 31.4fJ/conversion-step while dissipating 3.0mW from a 1.2V supply and occupying 0.059mm2.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; calibration; scaling circuits; CMOS SAR ADC; analog-digital conversion; capacitance scaling; digital calibration; dynamic threshold comparison; size 0.13 mum; successive-approximation-register; Bandwidth; CMOS technology; Calibration; Capacitors; Clocks; Latches; Metastasis; Prototypes; Sampling methods; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4244-6033-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2010.5433830
  • Filename
    5433830
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1883912