Title :
A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR
Author :
Wenbo Liu ; Pingli Huang ; Yun Chiu
Author_Institution :
Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA
Abstract :
A perturbation-based background digital calibration enables the capacitance scaling to the kT/C limit in a 12b SAR ADC. Combined with a dynamic threshold comparison technique, the 0.13¿m CMOS prototype measures a 71.1dB peak SNDR, a 94.6dB peak SFDR, and a peak FoM of 31.4fJ/conversion-step while dissipating 3.0mW from a 1.2V supply and occupying 0.059mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; scaling circuits; CMOS SAR ADC; analog-digital conversion; capacitance scaling; digital calibration; dynamic threshold comparison; size 0.13 mum; successive-approximation-register; Bandwidth; CMOS technology; Calibration; Capacitors; Clocks; Latches; Metastasis; Prototypes; Sampling methods; Switches;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433830
