A floating communication processor architecture in a distributed real-time system

Author

Shin, Kang G. ; Muthuswamy, Yogesh

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

Volume

1

fYear

1989

fDate

3-6 Jan 1989

Firstpage

120

Abstract

The issues involved in providing hardware communication support at each mode in a distributed real-time system are studied. First, a general architecture for each node of the system is described. An algorithm for message handling by dedicated hardware called a communication processor (CP) is proposed, to maximize the number of requests handled over the various constraints. A floating CP architecture is proposed, to maximize the number of requests handled under the various constraints. A floating CP architecture is proposed to maximize the utilization of the processors at a node and provide greater fault-tolerance in the system

Keywords

computer architecture; distributed processing; fault tolerant computing; real-time systems; dedicated hardware; distributed real-time system; fault-tolerance; floating communication processor architecture; hardware communication support; message handling; Bandwidth; Computer architecture; Concurrent computing; Data structures; Distributed computing; Fault tolerant systems; Hardware; Laboratories; Message passing; Real time systems;

fLanguage

English

Publisher

ieee

Conference_Titel

System Sciences, 1989. Vol.I: Architecture Track, Proceedings of the Twenty-Second Annual Hawaii International Conference on

Conference_Location

Kailua-Kona, HI

Print_ISBN

0-8186-1911-2

Type

conf

DOI

10.1109/HICSS.1989.47151

Filename

47151