Out-of-band asymmetry removal for high accuracy clock synchronization in 100Base-TX

The IEEE 1588 standard enables accurate clock synchronization in a distributed network by synchronizing multiple slave clocks to one master. To reduce the synchronization offset, IEEE 1588 compensates for the propagation delay between master and slave by round-trip measurements and the assumption of known link asymmetries. Yet, the determination of the asymmetries is out of scope of the standard. Therefore, state-of-the-art implementations often neglect the presence of asymmetry which leads to a clock offset between master and slaves. In this paper we propose an asymmetry determination method for 100Base-TX using out-of-band Chirp Spread Spectrum signaling. In contrast to the round-trip measurements by IEEE 1588 event messages, the proposed solution is able to measure each individual link delay and is therefore capable of resolving the asymmetry. The practical feasibility of the proposed solution is shown by an FPGA-based prototype solution, which reveals that our approach enables sub-nanosecond synchronization even over (asymmetric) CAT5 cabling.