Title :
A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS
Author :
Seon-Kyoo Lee ; Young-Hun Seo ; Yunjae Suh ; Hong-June Park ; Jae-Yoon Sim
Author_Institution :
Pohang Univ. of Sci. & Technol., Pohang, South Korea
Abstract :
A sub-exponent TDC performs power-efficient linear phase detection. With a cascaded chain of self-calibrated 2× time amplifiers, TDC generates the sub-exponent-only information for the fractional time difference. The TDC, implemented in a 0.18 μm CMOS, shows a minimum resolution of 1.25 ps with a total conversion range of 2.5 ns. When used in a DPLL, the rms jitter is 5 ps at 960 MHz output.
Keywords :
CMOS integrated circuits; phase locked loops; ADPLL; CMOS; all-digital phase locked loops; cascaded chain; complementary metal oxide semiconductor; frequency 1 GHz; frequency 960 MHz; minimum resolution sub-exponent TDC; power-efficient linear phase detection; size 0.18 μm; time 1.25 ps; time 2.5 ns; time 5 ps; Calibration; Clocks; Delay effects; Energy consumption; Inverters; Jitter; Linearity; Phase frequency detector; Phase locked loops; Testing;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433837
