A novel floating-point function unit combining MAF and 3-input adder

The multi-input floating-point (FP) adder is one of attractive solutions to accelerate algorithms including a lot of addition operations. However, a specialized multi-input adder will increase too much area to the floating-point unit. In this paper, we propose a novel FP function unit combing a 3-input FP adder with a traditional Multiply-Add-Fused (MAF) unit which is widely employed in many general processors and stream processors. Namely, the new FP function unit could perform both A × B + C and A + B + C. An improved architecture of the 3-input FP adder is proposed firstly which has the same accuracy with a FP adder that has an infinite internal width and only once rounding operation for two additions. Secondly, the architecture combining 3-input FP adder and Multiply-Add-Fused unit is presented which is compatible with IEEE-Std754. Lastly, the implementation results in single-precision data format are given with 180nm CMOS technology. Comparing with the MAF unit, the proposed function unit only increases delay and area by 2.8% and 30% respectively,which means the new function unit could accelerate A + B + C nearly 2 times than a MAF does. A small data format version of the proposed architecture has been verified by an exhaustive testing.