DocumentCode :
1884209
Title :
A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS
Author :
Borremans, Jonathan ; Vengattaramane, K. ; Giannini, V. ; Craninckx, Jan
Author_Institution :
IMEC, Leuven, Belgium
fYear :
2010
fDate :
7-11 Feb. 2010
Firstpage :
480
Lastpage :
481
Abstract :
A 86 MHz-12 GHz digital-intensive reconfigurable synthesizer is presented with 100 kHz to 2 MHz bandwidth. It leverages a 15 pJ/Shot 5.5 ps 14 b coarse-fine TDC and a 6-to-12 GHz dual-VCO set. The 0.28 mm2 synthesizer features simple background calibration, ¿¿ noise cancelation, and digital phase modulation, and consumes less than 30 mW.
Keywords :
CMOS digital integrated circuits; UHF circuits; VHF circuits; delta-sigma modulation; field effect MMIC; microwave circuits; phase locked loops; phase modulation; voltage-controlled oscillators; CMOS digital integrated circuit; coarse-fine TDC; digital phase modulation; digital-intensive reconfigurable synthesizer; dual-VCO set; frequency 86 MHz to 12 GHz; phase-modulated fractional-N PLL; simple background calibration; size 40 nm; time 5 ps; ¿¿ noise cancelation; Bandwidth; Calibration; Digital filters; Digital modulation; Monitoring; Noise cancellation; Phase locked loops; Phase noise; Synthesizers; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
978-1-4244-6033-5
Type :
conf
DOI :
10.1109/ISSCC.2010.5433840
Filename :
5433840
Link To Document :
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