Title :
Spur-reduction techniques for PLLs using sub-sampling phase detection
Author :
Xiang Gao ; Klumperink, Eric A. M. ; Socci, Gerard ; Bohsali, Mounir ; Nauta, Bram
Author_Institution :
Univ. of Twente, Enschede, Netherlands
Abstract :
A low-spur sub-sampling PLL exploits an amplitude-controlled charge pump which is immune to current source mismatch. A DLL/PLL dual-loop architecture and buffering reduces the disturbance of the sampler to the VCO. The 2.2GHz PLL in 0.18¿m CMOS achieves -121dBc/Hz in-band phase noise at 200kHz and consumes 3.8mW. The worst-case reference spur measured on 20 samples is -80dBc.
Keywords :
charge pump circuits; phase detectors; phase locked loops; PLL; amplitude-controlled charge pump; dual-loop architecture; frequency 2.2 GHz; frequency 200 kHz; power 3.8 mW; size 0.18 mum; spur-reduction techniques; sub-sampling phase detection; Clocks; Filters; Phase detection; Phase locked loops; Phase noise; Sampling methods; Steady-state; Switches; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433841
