Fine grain fault tolerance — A key to high reliability for FPGAs in space

Nowadays using SRAM-based FPGAs in space missions due to their flexibility and reprogrammability is on focus. In contrary, they are effective against radiation effects and need new trends in reliability issues. This paper concerns fine grain views to mitigation problem in FPGAs. For new FPGA generations simply replicating complete systems in Triple Modular Redundancy (TMR) technique may not be sufficient anymore. This especially applies to the environments like space, as higher failure rates may disrupt a second instance before the first one recovers. We focus on SEU mitigation challenges in SRAM-based FPGAs, which can result in crucial situations. The approach is a fine grain fault tolerance with using fine grain TMR also Quadruple Force Decide Redundancy (QFDR). We transform the classical concept of TMR and Quadded Redundancy on Logic Gates to a technological approach based on FPGA structure primitives like LUTs. We integrate common CAD tools to apply the techniques for different, complex designs simply. We simulate the faulty circuit and count the number of LUTs, which can be corrupted while the system still functions. Result shows the reliability increase of about 50 percent for QFDR.