Title :
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation
Author :
Zanuso, M. ; Levantino, Salvatore ; Samori, Carlo ; Lacaita, Andrea
Author_Institution :
Politec. di Milano, Milan, Italy
Abstract :
A 3.6 GHz digital fractional-N PLL combines a 4b TDC with digital element shuffling, and a 4b feedback phase interpolator with digital cancellation of mismatches. It achieves maximum in-band fractional spur of -57 dBc and in-band noise of -104 dBc/Hz at 400 kHz offset with 3 MHz bandwidth. The PLL draws 67 mA from a 1.2 V supply and occupies an active area of 0.4 mm2 in 6 nm CMOS.
Keywords :
CMOS integrated circuits; convertors; phase locked loops; CMOS; digital element shuffling; digital fractional-N PLL; digital mismatch cancellation; feedback phase interpolator; frequency 3 MHz; frequency 3.6 GHz; phase-interpolation divider; size 6 nm; subgate-delay TDC; time-to-digital converter; voltage 1.2 V; Bandwidth; Clocks; Delay lines; Frequency; Jitter; MOS capacitors; Noise cancellation; Phase locked loops; Quantization; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433842
