Title :
A calibration-free 800MHz fractional-N digital PLL with embedded TDC
Author :
Chen, Mike Shuo-Wei ; Su, Donglin ; Mehta, Sharad
Author_Institution :
Atheros Commun., Santa Clara, CA, USA
Abstract :
An 800 MHz digital PLL with its TDC embedded within the DVCO is implemented in 65 nm CMOS and occupies 0.027 mm2. The design requires no calibration and achieves the fractional-N operation without a multi-modulus feedback divider. To further improve the TDC linearity, mismatch filtering is used to achieve a DNL of less than 3.5% of LSB.
Keywords :
digital phase locked loops; calibration-free fractional-N digital PLL; embedded TDC; frequency 800 MHz; mismatch filtering; size 65 nm; Clocks; Delay; Delta-sigma modulation; Digital filters; Filtering; Frequency; Jitter; Phase locked loops; Resistors; Ring oscillators;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433844
