DocumentCode :
1884377
Title :
Next Generation Test Generator (NGTG) for digital circuits
Author :
Singer, Steven ; Vanetsky, Larry
Author_Institution :
NAWCAD, Lakehurst, NJ, USA
fYear :
1997
fDate :
22-25 Sep 1997
Firstpage :
105
Lastpage :
112
Abstract :
The process outlined in this paper describes the system developed to meet the goals of the Next Generation Test Generator program, funded by the Office of Naval Research. This system takes advantage of an unsupervised pattern classification algorithm (Adaptive Resonance Theory (ART)) and a Genetic Algorithm (GA) that is combined to form an optimizing control system. The GA generates a population of test patterns (individuals). Each individual is provided as a set of timed inputs to behavior based simulations representing good and faulty systems. The response of each model (good and faulty) is recombined in the form of an image matrix with each row representing a signature of each of the different circuits. FuzzyART (Fuzzy Logic Based ART) provides a method of image recognition, extracting those images that are distinctly different from any other. Each individual generated by the GA is provided as input to the list of models, then evaluated by FuzzyART and a fitness representing the number of separate classes is formed. New test sequences evolve with increasing fault isolation and detection. The process is repeated until a maximum number of models have been identified and separated. A selective breading algorithm was included to reduce the need for large populations, thus increasing the speed to converge to the “best test”. The process was demonstrated using a commercial simulator based on Verilog HDL with a simple master/slave flip-flop and a moderately complex digital circuit (real UUT)
Keywords :
automatic test equipment; circuit testing; digital circuits; digital simulation; fault location; fuzzy logic; genetic algorithms; image classification; image sequences; logic testing; software engineering; unsupervised learning; Adaptive Resonance Theory; Fuzzy Logic; Genetic Algorithm; Office of Naval Research; Verilog HDL; commercial simulator; complex digital circuit; digital circuits; image extraction; image matrix; image recognition; master/slave flip-flop; optimizing control system; selective breading algorithm; simulations; test patterns; unsupervised pattern classification algorithm; Circuit faults; Circuit simulation; Circuit testing; Classification algorithms; Digital circuits; Hardware design languages; Pattern classification; Programmable control; Subspace constraints; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
AUTOTESTCON, 97. 1997 IEEE Autotestcon Proceedings
Conference_Location :
Anaheim, CA
Print_ISBN :
0-7803-4162-7
Type :
conf
DOI :
10.1109/AUTEST.1997.633572
Filename :
633572
Link To Document :
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