• DocumentCode
    1884567
  • Title

    43Gb/s CP-QPSK Realtime Receiver Demonstrator based on FPGAs and block-processing

  • Author

    Geyer, Jonas C. ; Fludger, Chris R S ; Duthel, Thomas ; Presslein, Paul ; Schulien, Christoph ; Schmauss, Bernhard

  • Author_Institution
    Dept. of High Freq. Technol., Univ. of Erlangen, Erlangen, Germany
  • fYear
    2009
  • fDate
    20-24 Sept. 2009
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    We present measurement results of an FPGA-based 43 Gb/s Realtime Coherent Receiver Demonstrator. Due to limitations we use block-aggregation and process 1/32 of the input data stream. We show back-to-back performance and chromatic dispersion tolerance.
  • Keywords
    field programmable gate arrays; light polarisation; quadrature phase shift keying; receivers; CP-QPSK realtime receiver demonstrator; FPGA; block-aggregation; block-processing; chromatic dispersion tolerance; Assembly; Chromatic dispersion; Digital signal processing; Field programmable gate arrays; Frequency synchronization; Graphical user interfaces; Hardware; Polarization; Signal processing algorithms; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Optical Communication, 2009. ECOC '09. 35th European Conference on
  • Conference_Location
    Vienna
  • Print_ISBN
    978-1-4244-5096-1
  • Type

    conf

  • Filename
    5287155
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1884567