AVS video decoding acceleration on ARM Cortex-A with NEON

Author

Jie Wan ; Ronggang Wang ; Hao Lv ; Lei Zhang ; Wenmin Wang ; Chenchen Gu ; Quanzhan Zheng ; Wen Gao

Author_Institution

Shenzhen Grad. Sch., Sch. of Comput. & Inf. Eng., Peking Univ., Shenzhen, China

fYear

2012

fDate

12-15 Aug. 2012

Firstpage

290

Lastpage

294

Abstract

Acceleration of Audio Video coding Standard (AVS) Jizhun profile decoder has been proposed for ARM Cortex-A with NEON. Data level parallelism is utilized to effectively use the SIMD capability of NEON. Key modules are redesigned to make them SIMD friendly. Our optimized C implementation is set as start point for the acceleration. Thanks to effective use of ARM Cortex-Ax architecture and NEON SIMD engine, AVS decoding has been accelerated considerably. Results are provided for the overall acceleration in decoding and individual acceleration for key modules of AVS decoder.

Keywords

decoding; parallel architectures; video coding; ARM Cortex-A; AVS decoder; AVS video decoding acceleration; Jizhun profile decoder; NEON SIMD engine; audio video coding standard; data level parallelism; single instruction multiple data architecture; Acceleration; Computer architecture; Decoding; Interpolation; Registers; Streaming media; Transforms; ARM; AVS; NEON; SIMD; acceleration; video decoder;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing, Communication and Computing (ICSPCC), 2012 IEEE International Conference on

Conference_Location

Hong Kong

Print_ISBN

978-1-4673-2192-1

Type

conf

DOI

10.1109/ICSPCC.2012.6335736

Filename

6335736