Title :
Characterization of the faulted behavior of digital computers and fault tolerant systems
Author :
Bavuso, Salvatore J. ; Miner, Paul S.
Author_Institution :
NASA Langley Res. Center, Hampton, VA, USA
Abstract :
Research that is being conducted to characterize the latent fault in digital fault-tolerant systems is addressed. A series of investigations that have led to the development of a practical high-speed gate-level logic simulator is described. The validation of the high-speed simulator, using faultable software, and hardware simulations of a prototype MIS-STD-1750A processor are discussed
Keywords :
digital computers; fault tolerant computing; logic CAD; MIS-STD-1750A processor; characterization; digital computers; fault tolerant systems; faultable software; faulted behavior; high-speed gate-level logic simulator; Application software; Circuit faults; Computational modeling; Fault detection; Fault tolerant systems; Hardware; Logic devices; Logic testing; Microprocessors; Very large scale integration;
Conference_Titel :
System Sciences, 1989. Vol.I: Architecture Track, Proceedings of the Twenty-Second Annual Hawaii International Conference on
Conference_Location :
Kailua-Kona, HI
Print_ISBN :
0-8186-1911-2
DOI :
10.1109/HICSS.1989.47155
