ES5: Can RF SoCs (Self)test their own RF?

RF testing is an increasingly critical component of modern RF SoC´s. While digital logic and memory tests have all become largely automated and inexpensive through built-in self-test (BIST), testing for RF parameter compliance of a wireless standard is time consuming and commands a significant fraction of the total SoC cost. Due to the conventional need for large and expensive RF test equipment, these tests limit the SoC manufacturing throughput (about 3 million cell phones are manufactured per day!) and cannot accommodate other parts of SoC lifecycles, such as on-wafer testing. At the same time, the stakes are much higher in RF SoC´s: A failing RF circuit means throwing away the perfectly working digital/memory section occupying most of the die. Recent publications have proposed to exploit the increasing abundance and intelligence of the on-die digital logic to test its RF part in order to reduce the complexity of external test equipment or even eliminate it entirely. With the external equipment bottleneck gone, massively- parallel tests of hundreds or thousands of IC chips can be carried out simultaneously, thus greatly reducing the average test time. Although it imposes limitations, the self-testing can open up new avenues, such as on-wafer or on-die (i.e., pre-packaging) and in-field (i.e., during customer use) verification of RF performance. Since RF-BIST is about manipulating internal signals, it could naturally assist with RF performance to improve parametric yield so that effective yield approaches that of defect density. Digital designers have mastered BIST long ago and now it is time for the RF community to embrace similar ideas. RF circuit and system designers need to pay close attention to it: Self-testing will affect the selection of RF front-end circuitry and architecture so it cannot be merely viewed as something confined to the back-end sections of a modem.