An efficient single copy cache coherence protocol for multiprocessors with multistage interconnection networks

Multistage interconnection networks offer an efficient, scalable, and cost effective solution for the problem of connecting processors to memory in a shared memory multiprocessor system. In this paper, we present an efficient single copy cache coherence protocol for multiprocessors with multistage interconnection networks. Our protocol depends on incorporating the cache memory into the switches (caching switches) of the multistage interconnection network. In our proposed protocol, data blocks move between the switches in order to minimize the memory access time. We also develop a migration policy for data blocks not only to minimize the average memory response time but also to minimize the overhead in locating a specific memory block in case of a cache miss. We use two variations of our proposed protocol, the first allows caches to be only in the caching switches in the second of the interconnection network, while the first allows the caches to be in any switch of the interconnection network. We use simulation to evaluate the performance of our protocol and compare it with two multiple copy cache coherence protocols designed for systems employing multistage interconnection networks. The simulation results indicate that our proposed protocol outperforms the distributed write and distributed invalidate protocols for a wide range of memory access patterns