DocumentCode :
1885508
Title :
Session 19 overview: High-performance embedded memory
Author :
Pilo, Harold ; Zhang, Kevin
Author_Institution :
IBM, Essex Junction, VT, USA
fYear :
2010
fDate :
7-11 Feb. 2010
Abstract :
Among all integrated circuits, embedded memory has truly become pervasive and plays an essential role in all of today´s VLSI applications such as high-performance computing, low-power and ubiquitous consumer electronics. The rapid reduction of feature size has made it possible to integrate larger and higher performance on-die memories for various logic applications. Technology scaling also creates growing challenges for the embedded memory designer. It is increasingly difficult to scale density while maintaining adequate cell margins for robust read and write operations. The degradation of intrinsic cell design margins, induced by growing device variations, has led to innovative design solutions to overcome these challenges. Among them, advanced peripheral circuit techniques to improve read and write margins have been explored extensively with focus on more intelligent use of power supplies. On-die adaptive design techniques that automatically compensate process-voltage-temperature (PVT) variations are also emerging to further improve the design robustness for high-volume manufacturing requirements. While improving and optimizing the transistor characteristics in SRAMs, 1T1C-based DRAM technology (eDRAM) has made significant progress in recent years and it is successfully integrated into leading logic processes. After years of promise, an eDRAM-based large on-die cache now has finally arrived in a high-performance microprocessor.
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
ISSN :
0193-6530
Print_ISBN :
978-1-4244-6033-5
Type :
conf
DOI :
10.1109/ISSCC.2010.5433888
Filename :
5433888
Link To Document :
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