A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

Author

Tae-Young Oh ; Young-Soo Sohn ; Seung-Jun Bae ; Min-Sang Park ; Ji-Hoon Lim ; Yong-Ki Cho ; Dae-Hyun Kim ; Dong-Min Kim ; Hye-Ran Kim ; Hyun-Joong Kim ; Jin-Hyun Kim ; Jin-Kook Kim ; Young-Sik Kim ; Byeong-Cheol Kim ; Sang-Hyup Kwak ; Jae-Hyung Lee ; Jae-

Author_Institution

Samsung Electron., Suwon, South Korea

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

434

Lastpage

435

Abstract

7 Gb/s/pin operation without bank group restriction in a GDDR5 SDRAM is achieved by skewed control logic and current-mode I/O sense amplifiers with regular calibration from replica impedance monitors. The bank-to-bank active time is shortened to 2.5 ns by a FIFO-based BLSA enabler, 2.0 ns latency V_PP generator and active jitter canceler. The chip is fabricated in a 50 nm DRAM process in a 61.6 mm² die area.

Keywords

DRAM chips; amplifiers; calibration; current-mode circuits; jitter; FIFO-based BLSA enabler; GDDR5 SDRAM; VPP generator; active jitter canceler; bank-to-bank active time; current-mode I/O sense amplifiers; no bank-group restriction; regular calibration; replica impedance monitors; size 50 nm; skewed control logic; time 2 ns; time 2.5 ns; Boosting; Charge pumps; Delay; Jitter; Operational amplifiers; Pulse amplifiers; Random access memory; SDRAM; Timing; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5433889

Filename

5433889