A host interface architecture for HIPPI

High performance communication in the gigabit range can cause the end host to be the bottleneck. To relieve the host from the processing requirements of gigabit communication, specialized hardware is needed in the host interface. At the aggregate HIPPI input and output peak rate of 1.6 Gb/s, the major bottlenecks are in moving the data between the host´s memory and the I/O channels, and in meeting the requirements of the physical protocol. An architecture that solves these problems is implemented on the HIPPI node of the Paragon Supercomputer. The architecture is highly parallel to facilitate in transferring the data at high speeds and in handling the requirements of the HIPPI physical protocol. Dedicated hardware is implemented for fast connect/disconnect to utilize the channel bandwidth efficiently