A methodology to evaluate the aging impact on flip-flops performance

Author

Nunes, C. ; Butzen, Paulo F. ; Reis, Andre I. ; Ribas, Renato P.

Author_Institution

Inst. of Inf., Fed. Univ. of Rio Grande do Sul-UFRGS, Porto Alegre, Brazil

fYear

2013

fDate

2-6 Sept. 2013

Firstpage

1

Lastpage

6

Abstract

The impact of aging effects, in terms of circuit performance and reliability, is one of the new recent challenges in VLSI design targeting the most advanced CMOS technologies. This work proposes an effective methodology to aging analysis in flip-flops. The estimation method proposed previously for combinational logic gates is exploited and improved herein to address such sequential gates. Three different conventional static flip-flops have been used as case studies to demonstrate and validate the proposed methodology.

Keywords

CMOS logic circuits; ageing; combinational circuits; flip-flops; integrated circuit reliability; negative bias temperature instability; semiconductor device breakdown; sequential circuits; CMOS technologies; TDDB; VLSI design; aging impact; bias temperature instability; combinational circuits; hot carrier injection; integrated circuit reliability; sequential gates; static flip-flops; time dependent dielectric breakdown; transistor degradation; very large scale integration; Aging; Degradation; Flip-flops; Human computer interaction; Logic gates; Threshold voltage; Transistors; BTI; CMOS; Digital circuit; HCI; TDDB; aging; flip-flop; performance; reliability;

fLanguage

English

Publisher

ieee

Conference_Titel

Integrated Circuits and Systems Design (SBCCI), 2013 26th Symposium on

Conference_Location

Curitiba

Type

conf

DOI

10.1109/SBCCI.2013.6644860

Filename

6644860