Delay model for static CMOS complex gates

This paper presents a novel approach for delay modeling of CMOS complex gates, containing series and parallel transistor arrangements. The model uses a charge based approach instead of evaluating voltages as function of time. The impact of input transition time, input-to-output coupling capacitance and short-channel effects, such as drain-induced barrier lowering (DIBL) and velocity saturation, are taken into account. The only empirical parameters are those required to calibrate the transistor model. Analytical results are in good agreement with HSPICE simulation data, based on BSIM4 transistor model, over a wide range of input slopes and output loads. Additionally, model accuracy has been improved when compared to previous related work.