Test power aware STUMP BIST

Author

Gowthami, M.R. ; Kiran, N. Ravi ; Harish, G. ; Yellampalli, Siva

Author_Institution

VLSI Dept., UTL Technol. Ltd., Bangalore, India

fYear

2015

fDate

6-8 May 2015

Firstpage

434

Lastpage

438

Abstract

The testing power is the biggest concern in modern VLSI chip testing which affects the reliability of the chip. The testing power is very greater than the functional power because during the test mode almost all the part of the chip is active which elevates the testing power problem. In this paper a low test power BIST architecture is proposed which employs clock gating and scan staggering to reduce the testing power, and scan chain segmentation to reduce the testing time. From the experiments conducted on ISCAS89 benchmark circuits, the proposed BIST architecture reduces the test power by 56% with 1% area overhead.

Keywords

VLSI; built-in self test; clocks; integrated circuit testing; low-power electronics; ISCAS89 benchmark circuits; clock gating; functional power; low test power BIST architecture; modern VLSI chip testing; scan chain segmentation; scan staggering; test mode; test power aware STUMP BIST; testing power problem; testing time; Benchmark testing; Built-in self-test; Clocks; Computer architecture; Logic gates; Very large scale integration; Automatic test equipment (ATE); Built in Self-test (BIST); Circuit Under Test (CUT); Linear Feedback Shift Register (LFSR); Multiple Input Signature Register (MISR); Scan enable (SE); Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS); System on Chip (SoC); Test pattern generator (TPG);

fLanguage

English

Publisher

ieee

Conference_Titel

Smart Technologies and Management for Computing, Communication, Controls, Energy and Materials (ICSTM), 2015 International Conference on

Conference_Location

Chennai

Print_ISBN

978-1-4799-9854-8

Type

conf

DOI

10.1109/ICSTM.2015.7225456

Filename

7225456