A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS

Author

Agarwal, Abhishek ; Mathew, Sanu K. ; Hsu, S.K. ; Anders, Mark A. ; Kaul, Himanshu ; Sheikh, Farhana ; Ramanarayanan, R. ; SRINIVASAN, SUDARSHAN ; Krishnamurthy, Ram ; Borkar, Shekhar

Author_Institution

Intel, Hillsboro, OR, USA

fYear

2010

fDate

7-11 Feb. 2010

Firstpage

328

Lastpage

329

Abstract

A 32 nm on-die fine-grained reconfigurable fabric for DSP/media accelerators is fabricated and occupies a 0.076 mm² die. The optimized hybrid arithmetic configurable logic blocks with self-decoded look-up tables, ultra-low voltage PVT-tolerant register file circuits and dual-supply operation help enable a 2.4 GHz nominal performance at 1.0 V and 320 mV-to-1.2 V dynamic voltage range. The peak energy efficiency is 2.6TOPS/W when measured at 340 mV and 50Â°C.

Keywords

CMOS integrated circuits; UHF integrated circuits; digital signal processing chips; logic design; reconfigurable architectures; table lookup; CMOS; DSP; frequency 2.4 GHz; hybrid arithmetic configurable logic blocks; media accelerators; on-die fine-grained reconfigurable fabric; self-decoded look-up tables; size 32 nm; temperature 50 C; ultra-low voltage PVT-tolerant register file circuits; voltage 320 mV to 1.2 V; Arithmetic; CMOS logic circuits; Digital signal processing; Dynamic range; Energy efficiency; Fabrics; Logic circuits; Reconfigurable logic; Registers; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International

Conference_Location

San Francisco, CA

ISSN

0193-6530

Print_ISBN

978-1-4244-6033-5

Type

conf

DOI

10.1109/ISSCC.2010.5433903

Filename

5433903