• DocumentCode
    1886114
  • Title

    A 59.5mW scalable/multi-view video decoder chip for Quad/3D Full HDTV and video streaming applications

  • Author

    Tzu-Der Chuang ; Pei-Kuei Tsung ; Pin-Chih Lin ; Lo-Mei Chang ; Tsung-Chuan Ma ; Yi-Hau Chen ; Liang-Gee Chen

  • Author_Institution
    Nat. Taiwan Univeristy, Taipei, Taiwan
  • fYear
    2010
  • fDate
    7-11 Feb. 2010
  • Firstpage
    330
  • Lastpage
    331
  • Abstract
    A 90 nm 59.5 mW scalable/multi-view/H.264 multi-standard video decoder chip is implemented in a 8.53 mm2 die. Via a throughput-efficiency architecture with reconfigurable scheduling and a cache system, a low memory bandwidth, high-throughput design is achieved. It has 3.41x throughput with 47% power reduction compared to previous work.
  • Keywords
    codecs; high definition television; video coding; video streaming; H.264 video coding; power 59.5 mW; quad/3D full HDTV; scalable multi-view video decoder chip; size 90 nm; video streaming applications; Decoding; Delay; Design optimization; HDTV; Random access memory; Scalability; Static VAr compensators; Streaming media; Throughput; Video coding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4244-6033-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2010.5433908
  • Filename
    5433908
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1886114