• DocumentCode
    1886279
  • Title

    A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications

  • Author

    Meng-Fan Chang ; Shu-Meng Yang ; Chih-Wei Liang ; Chih-Chyuang Chiang ; Pi-Feng Chiu ; Ku-Feng Lin ; Yuan-Hua Chu ; Wen-Chin Wu ; Yamauchi, Hiroyuki

  • Author_Institution
    Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • fYear
    2010
  • fDate
    7-11 Feb. 2010
  • Firstpage
    266
  • Lastpage
    267
  • Abstract
    A 90 nm 256 Kb NAND-ROM using read-1 noise elimination and read-0 sensing-margin-expanding schemes is functional at 0.29 V and 3 MHz with 100% code-coverage and 5% area overhead. This work reduces the delay-per-BL-length, energy-per-bit at VDDmin, and VDDmin-delay-product by 3000×, 4× and 3700×, respectively, compared to previous low-voltage ROMs.
  • Keywords
    CMOS memory circuits; NAND circuits; low-power electronics; read-only storage; CMOS; bandwidth 3 MHz; embedded NAND-ROM; low-voltage ROM; noise elimination; read-0 sensing-margin-expanding schemes; size 90 nm; storage capacity 256 Kbit; ultralow-voltage applications; voltage 0.29 V; CMOS memory circuits; CMOS process; Capacitors; Crosstalk; Decision support systems; Feedback circuits; Laser sintering; Nonvolatile memory; Read only memory; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4244-6033-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2010.5433914
  • Filename
    5433914
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1886279