A methodology for the automatic design of operational amplifiers including yield optimization

This paper presents an automatic sizing methodology for CMOS operational amplifiers considering process parameter variations in submicron technologies. These circuits are very sensitive to process variations, which cause mismatch. The proposed methodology comprises simultaneous optimization of power dissipation, gate area and yield prediction, exploring effectively the design space in all transistor operation regions. Yield is estimated by Monte Carlo analysis, which is performed only for the best solutions candidates in the optimization procedure. A Miller OTA and a folded cascode amplifier are designed in 0.18μm technology using the proposed methodology. Results show the increase in the circuit yield comparing to the same design without yield prediction, while keeping the power and area budget and a reasonable computational time.