Title :
A 2Gb/s network processor with a 24mW IPsec offload for residential gateways
Author :
Nishida, Yoshiharu ; Kawai, Kunihiro ; Koike, K.
Author_Institution :
NTT, Japan
Abstract :
A 90 nm CMOS network processor comprising dual CPUs, a packet engine (PE), and an embedded LAN switch is developed on a 7.51 × 7.75 mm2 die. The network processors enable a residential gateway to forward packets at 2 Gb/s with IP security and packet filtering. By offloading the packet handling to a packet engine, the power consumption of this function is limited to 24 mW.
Keywords :
CMOS digital integrated circuits; IP networks; embedded systems; internetworking; local area networks; microprocessor chips; CMOS network processor; IP security; IPsec Offload; PE; embedded LAN switch; network processor; packet engine; packet filtering; power consumption; residential gateways; Authentication; Buffer storage; Circuits; Fluctuations; Local area networks; Logic; Packet switching; Switches; Throughput; Wide area networks;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433917
