Design, fabrication and evaluation of deep submicron FETs

GaAs FET´s with gatelengths on a nanometer scale have been designed, fabricated and evaluated in order to investigate the limits of conventional GaAs scaling rules. An optimum layer structure for deep submicron GaAs MESFETs was designed, and a fabrication process that minimizes the effects of extrinsic parasitics was developed. The fabricated FETs were measured and evaluated at DC and at RF frequencies. 0.1 μm and 50 nm gatelength GaAs MESFETs with 2×45 μm wide T-shaped gates were fabricated so that a wide range of saturation current was achieved. For the 0.1 μm gatelength FETs, peak g_m,ext varies from 611 mS/mm to 795 mS/mm with an average value of 717 mS/mm, peak f_t varies from 90 GHz to 103 GHz with an average value of 96 GHz, and peak f_max varies from 147 GHz to 172 GHz with an average value of 161 GHz. In comparison, the peak g_m,ext of the 50 nm gatelength FETs is reduced by almost 20%, the peak f_t is increased by 30%, and the peak f_max is about the same as for the 0.1 μm gatelength FETs. The f_t of the 50 nm gatelength FETs is higher than the f_t of the 0.1 μm gatelength FETs because of the reduced gate-source capacitance (C_gs). The peak f_max does not show a similar improvement because of the onset of short channel effects