DocumentCode
1886546
Title
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS
Author
Verbruggen, Bob ; Craninckx, Jan ; Kuijk, Maarten ; Wambacq, Piet ; Van der Plas, G.
Author_Institution
IMEC, Leuven, Belgium
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
296
Lastpage
297
Abstract
A 2.2 GS/S 4×-interleaved 6b ADC in 40 nm digital CMOS is presented. Each ADC slice consists of a 1b folding stage followed by a pipelined binary-search sub-ADC using dynamic nonlinear amplifiers for low power consumption and high speed. Threshold calibration corrects for amplifier and comparator imperfections and 31.6 dB SNDR is achieved with 2 GHz ERBW for 2.6 mW power consumption.
Keywords
CMOS digital integrated circuits; amplifiers; analogue-digital conversion; calibration; comparators (circuits); low-power electronics; 1b folding stage; bit rate 2.2 Gbit/s; comparator imperfections; digital CMOS; dynamic nonlinear amplifiers; frequency 2 GHz; interleaved fully dynamic pipelined ADC; low power consumption; pipelined binary-search sub-ADC; power 2.6 mW; size 40 nm; threshold calibration; Calibration; Capacitance; Capacitors; Circuits; Clocks; Frequency; Sampling methods; Switches; Timing; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433925
Filename
5433925
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