Parallel hardware design for snake models with an FPGA architecture

Summary form only given. A hardware implementation for active contour models (snakes) using a numerical algorithm and an FPGA architecture is proposed. We introduce a digital implementation of discrete snake models and then propose an FPGA implementation based on use of a number of parallel cell units for snake points and a main controller for all control tasks and main memory access. Each cell unit contains three parallel processing elements (PE) including three internal small memories for updating each snake point within a neighborhood of pixels. Using this parallel architecture we could obtain a snake generation time of 28 ms in VGA image size (640/spl times/480 pixels) which was used for motion detection in video samples of 24 fps. The performance results are very encouraging however the system can be still improved by using more parallel processing units and simplifying some complicated instructions.