DocumentCode
1886648
Title
A 2Gb/s 1.8pJ/b/chip inductive-coupling through-chip bus for 128-Die NAND-Flash memory stacking
Author
Saito, Masato ; Miura, Naruhisa ; Kuroda, Tadahiro
Author_Institution
Keio Univ., Yokohama, Japan
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
440
Lastpage
441
Abstract
128 NAND Flash memory chips and 1 controller chip are stacked using a spiral stair stacking scheme. The controller accesses a random memory chip at 2 Gb/s by inductive-coupling through-chip transmission relayed at every 8th chip. The large coils are placed diagonally over memory core with no area penalty. Energy consumption is reduced to 1.8 pJ/b/chip.
Keywords
NAND circuits; coupled circuits; flash memories; integrated circuit interconnections; system buses; NAND flash memory stacking; bit rate 2 Gbit/s; controller chip; inductive coupling through chip bus; random memory chip; spiral stair stacking; through chip transmission; Bonding; Coils; Relays; Repeaters; Semiconductor device measurement; Spirals; Stacking; Testing; Transceivers; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5433929
Filename
5433929
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