Title :
A mostly digital variable-rate continuous-time ADC ΔΣ modulator
Author :
Taylor, Gareth ; Galton, Ian
Author_Institution :
Univ. of California, San Diego, CA, USA
Abstract :
A mostly digital variable-rate continuous-time ΔΣ modulator is presented with power dissipation, output sample-rate, bandwidth, and peak SNDR ranges of 8 to 17 mW, 0.5 to 1.15 GHz, 3.9 to 18 MHz, and 67 to 78 dB, respectively. The IC is implemented in a 65 nm CMOS process with an active area of 0.07 mm2.
Keywords :
CMOS integrated circuits; UHF integrated circuits; analogue-digital conversion; delta-sigma modulation; ΔΣ modulator; ADC modulator; CMOS; digital variable-rate continuous-time modulator; frequency 0.5 GHz to 1.15 GHz; frequency 3.9 MHz to 18 MHz; power 8 mW to 17 mW; size 65 nm; Calibration; Circuits; Clocks; Decoding; Digital modulation; Feedback; Frequency; Pulse width modulation inverters; Quantization; Ring oscillators;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433930
