Title :
A 17.5-to-20.94GHz and 35-to-41.88GHz PLL in 65nm CMOS for wireless HD applications
Author :
Richard, O. ; Siligaris, Alexandre ; Badets, F. ; Dehos, Cedric ; Dufis, C. ; Busson, Pierre ; Vincent, Pierre ; Belot, Didier ; Urard, P.
Author_Institution :
STMicroelectronics, Crolles, France
Abstract :
A complete frequency synthesizer occupying 1.1 mm2 in 65 nm CMOS is presented. It is composed of a push-push quadrature VCO that delivers two L0 signals in 20 and 40 GHz bands. The PLL consumes 80 mW including buffers, and achieves a phase noise lower than -100 and -97.5 dBc/Hz for the 20 GHz and the 40 GHz signals, respectively.
Keywords :
CMOS integrated circuits; field effect MIMIC; frequency synthesizers; phase locked loops; voltage-controlled oscillators; CMOS technology; PLL; frequency 17.5 GHz to 20.94 GHz; frequency 35 GHz to 41.88 GHz; frequency synthesizer; power 80 mW; push-push quadrature VCO; size 65 nm; wireless HD applications; Filters; Frequency conversion; Frequency synthesizers; High definition video; Phase frequency detector; Phase locked loops; Semiconductor device measurement; Varactors; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433941
