• DocumentCode
    1887083
  • Title

    A 0.13µm 64Mb multi-layered conductive metal-oxide memory

  • Author

    Chevallier, C.J. ; Chang Hua Siau ; Lim, S.F. ; Namala, S.R. ; Matsuoka, Masashi ; Bateman, B.L. ; Rinerson, D.

  • Author_Institution
    Unity Semicond., Sunnyvale, CA, USA
  • fYear
    2010
  • fDate
    7-11 Feb. 2010
  • Firstpage
    260
  • Lastpage
    261
  • Abstract
    A 64Mb NAND-compatible non-volatile memory testchip based on a conductive metal-oxide technology is developed in 0.13μm technology. The memory cell, which does not require a selection device, occupies 0.17μm2 and is built at the intersection of two metal lines above the CMOS circuitry. The chip uses 4 layers of cross-point arrays. Decoding and sensing techniques are also described.
  • Keywords
    CMOS memory circuits; NAND circuits; random-access storage; CMOS circuitry; NAND-compatible nonvolatile memory testchip; decoding; multilayered conductive metal-oxide memory; sensing technique; size 0.13 micron; Circuits; Conducting materials; Degradation; Electrodes; Latches; Leakage current; Nonvolatile memory; Random access memory; Testing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4244-6033-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2010.5433945
  • Filename
    5433945
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1887083