Drop testing and finite element simulation of stacked chip scale packages with and without underfill

Drop testing is performed on stacked chip scale packages in eight configurations, including the use of two types of commercially available underfills. Full failure analysis using techniques such as dye penetrant and scanning electron microscopy (SEM) is performed. Corresponding explicit finite element simulations are performed using ANSYSreg LS-DYNA. These simulations are used to determine a suitable damage parameter and consequently, drop test life correlations are constructed. Considerable differences in drop impact reliability between Sn63Pb37 and SAC305 solder are observed.