Author :
Marotta, G.G. ; Macerola, A. ; d´Alessandro, Antonio ; Torsi, A. ; Cerafogli, C. ; Lattaro, C. ; Musilli, C. ; Rivers, D. ; Sirizotti, E. ; Paolini, F. ; Imondi, G. ; Naso, G. ; Santin, G. ; Botticchio, L. ; De Santis, Luca ; Pilolli, L. ; Gallese, M.L. ;
Abstract :
A 3.3V 32Gb NAND-Flash memory with 3b/cell is demonstrated in 34nm technology. The device features a programming throughput of 6MB/s on blocks configured as 3b/cell mode and can dynamically switch up to 13MB/s in 2b/cell mode. A new quad-plane architecture and an optimized programming algorithm are adopted to achieve the design targets.
Keywords :
flash memories; logic gates; nanoelectronics; NAND flash memory; bit rate 6 Mbit/s; block configuration mode; optimized programming algorithm; program throughput; quad-plane architecture; size 34 nm; storage capacity 32 Gbit; Charge pumps; Circuits; EPROM; Registers; Regulators; Resistors; Shape control; Temperature sensors; Throughput; Voltage;
