Title :
A maximally-digital radio receiver front-end
Author_Institution :
Audax Technol., Leuven, Belgium
Abstract :
A radio receiver with reduced analog circuits contains two ADCs placed immediately after the mixers. All filtering, offset compensation and variable gain are realised in the digital domain. The overall receiver chain, including ADCs, consumes 12 mW and occupies 0.07 mm2 in a 40 nm standard digital CMOS technology.
Keywords :
digital radio; radio receivers; CMOS technology; maximally-digital radio receiver front-end; offset compensation; overall receiver chain; reduced analog circuits; variable gain; Circuits; Clocks; Finite impulse response filter; Frequency; Inverters; Phase noise; Receivers; Ring oscillators; Signal to noise ratio; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433952
