Nano-scaled SRAM thermal stability analysis using hierarchical compact thermal models

Non-uniform temperature profile generated by hot- spots affect the nearby units in a chip. Different sections of a large sized cache memory would experience different failure statistics due to their proximity to the hot-spots. The nano-scaled SRAM (Static Random Access Memory) cell stability is analyzed systematically under such ´spatial´ temperature variations for different technologies. The bitcell level compact thermal models are generated for 65 nm, 45 nm, 32 nm and 22 nm bulk CMOS technology nodes based on the 6 T ´thin-cell´ structure. Next, the block level and system level ´macro´ thermal models are generated hierarchically for each technology node. A prominent effect ´leakage induced stability degradation´ is observed at 22 nm node. This work demonstrates that leakage reduction techniques should consider temperature/stability aspects in nano-scaled SRAM cells.