Title :
A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS
Author :
Furuta, Mamoru ; Nozawa, M. ; Itakura, T.
Author_Institution :
Toshiba, Kawasaki, Japan
Abstract :
An 8.9-ENOB 40MS/s two-stage pipelined SAR ADC for a WLAN receiver is designed and fabricated in a 65 nm CMOS technology. The 1st stage is realized by a 1.5b/cycle SAR to mitigate the comparator offset issue. The 2nd stage employs a radix-1.8 SAR to avoid the parasitic capacitance issue. The presented architecture occupies 0.06 mm2 of area despite using a large unit capacitance of 60fF.
Keywords :
CMOS integrated circuits; analogue-digital conversion; CMOS technology; ENOB; WLAN receiver; comparator offset; size 65 nm; two-stage pipelined SAR ADC; Capacitors; Circuits; Energy consumption; Frequency; Parasitic capacitance; Power amplifiers; Sampling methods; Switches; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5433968
