A Parallel Feedback Carry Adder Based on Half Adder

Author

Sheng Liyuan ; Jiang Wenming ; Tong Shuai ; Zhang Zhanfeng ; Cao Hua

Author_Institution

Sch. of Phys. Sci. & Technol., Central South Univ., Changsha, China

fYear

2010

fDate

25-26 Dec. 2010

Firstpage

1

Lastpage

4

Abstract

This paper proposes a new theory of adder and its basic structure. The new adder is an asynchronous adder whose basic unit is half adder, called Parallel Feedback Carry Adder (PFCA) as its carry mode is parallel feedback. In theory, compared to the adders (e.g. RCA, CLA, CSeA) based on full adder, PFCA is faster in speed and smaller in area. A CMOS gate implementation is proposed to verify the new design theory in this paper. HSPICE simulation results show that PFCA has obvious advantage over RCA, CLA, CSeA in speed and area, showing potential applications especially when adder bits n is larger.

Keywords

CMOS logic circuits; SPICE; adders; asynchronous circuits; carry logic; circuit feedback; logic design; CMOS gate; HSPICE simulation; asynchronous adder; carry mode; design theory; full adder; half adder; parallel feedback carry adder; Adders; Bismuth; CMOS integrated circuits; Delay; Hardware; Logic gates; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Engineering and Computer Science (ICIECS), 2010 2nd International Conference on

Conference_Location

Wuhan

ISSN

2156-7379

Print_ISBN

978-1-4244-7939-9

Electronic_ISBN

2156-7379

Type

conf

DOI

10.1109/ICIECS.2010.5677796

Filename

5677796