Title :
A 1.2 TB/s on-chip ring interconnect for 45nm 8-core enterprise Xeon® processor
Author :
Cheolmin Park ; Badeau, Roland ; Biro, L. ; Chang, Joana ; Singh, Taranveer ; Vash, J. ; Bo Wang ; Wang, Tao
Author_Institution :
Intel, Hudson, MA, USA
Abstract :
A 1.2 TB/s ring interconnect implemented with a 9 metal 45 nm technology is described. The implementation provides on-die communication for 8 Xeon cores, 8-port parallel-access 24 MB L3 cache, and 2 system-interface ports. The efficient, flexible, and modular building-block approach used to construct our design is described.
Keywords :
cache storage; integrated circuit interconnections; microprocessor chips; 2 system-interface ports; 8-core Enterprise Xeon® processor; 8-port parallel-access; L3 cache; bit rate 1.2 Tbit/s; modular building-block; on-chip ring interconnect; on-die communication; size 45 nm; Bandwidth; Capacitance; Clocks; Delay; Encoding; Integrated circuit interconnections; Logic; Microprocessors; Routing; Wire;
Conference_Titel :
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location :
San Francisco, CA
Print_ISBN :
978-1-4244-6033-5
DOI :
10.1109/ISSCC.2010.5434000
