VLSI array processors for linear-phase FIR filters

Array processor implementations are obtained (using the signal flow graph) for linear-phase FIR filters. Three structures are reported in which the inputs are pipelined and/or broadcast and the outputs are pipelined. A novel structure is obtained in which the outputs are localized in separate processing elements. A comparison among the resulting structures is performed based on the sampling rate, the latency, and the communication overhead perspectives. A new fixed-point array-multiplier design is then presented. The new processor can perform an add-multiply-accumulate operation in the same time as a simple multiplier. It increases the speed of operation without incurring extra silicon area or introducing extra latency to the system