VLSI implementation of rake receiver for IS-95 CDMA testbed using FPGA

In this work, an implementation of a time-multiplexed downlink Rake receiver complying with the IS-95 CDMA standard is presented. A low power architecture of the Rake receiver is implemented. A structure which provides the offset changing for the pseudo-random sequence (PN sequence) used for despreading of the CDMA signals is discussed. Architecture for the efficient time multiplexing of the Rake fingers is also presented. The design was implemented using Xilinx FPGA. It was tested to be functionally correct and the performance complied with IS-95.