DocumentCode
1888711
Title
Low-skew clock distribution using zero-phase-clock-buffer DLLs
Author
Ting Wu ; Aryanfar, Farshid ; Hae-Chang Lee ; Jie Shen ; Chin, Tat-Jun ; Werner, Claudia ; Chang, Kuo-Pin
Author_Institution
Rambus, Los Altos, CA, USA
fYear
2010
fDate
7-11 Feb. 2010
Firstpage
176
Lastpage
177
Abstract
A clock distribution scheme based on a zero-phase-clock-buffer (ZPCB) is presented. Each ZPCB generates an equal phase between its input and output by adjusting its resonant frequency to slightly higher than the clock frequency. A testchip fabricated in a 40 nm LP process measures sub-psec skew over 500 MHz and 800 MHz ranges, for a 5 GHz single-ended and a 15 GHz differential ZPCB, respectively.
Keywords
clocks; delay lock loops; integrated circuit testing; DLL; delay locked loops; differential ZPCB; frequency 15 GHz; frequency 5 GHz; frequency 500 MHz to 800 MHz; low skew clock distribution; resonant frequency; test chip fabrication; zero phase clock buffer; Circuit testing; Clocks; Digital control; Inductors; Inverters; Q factor; Resonance; Resonant frequency; Semiconductor device measurement; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
Conference_Location
San Francisco, CA
ISSN
0193-6530
Print_ISBN
978-1-4244-6033-5
Type
conf
DOI
10.1109/ISSCC.2010.5434002
Filename
5434002
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