VLSI implementation of a switch fabric for mixed ATM and IP traffic

Author

Tsui, Chi-ying ; Chung-Yin Kwan, Louis ; Lea, Chin-Tau

Author_Institution

Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Hong Kong

fYear

2000

fDate

9-9 June 2000

Firstpage

5

Lastpage

6

Abstract

A VLSI implementation of a multistage self-routing ATM switch fabric is presented. The size of the switch is 16/spl times/16 and can handle the OC-12 (622 Mbps) link rate. Based on a bit-slice architecture, the entire 16/spl times/16 switch is implemented using four identical chips. The switch hits multiple paths, created by a randomizer in front of the routing stages between each input-output pair. The switch uses an input/output-buffering scheme and contains no buffers inside the fabric. A priority structure, which supports four levels, allows the delay sensitive ATM cells to be switched with the shortest latency. It also enables the noninterleaving routing scheme of IP cells. The switch fabric was designed and fabricated using MOSIS 0.8 /spl mu/m technology and was tested to run at 93 MHz with 3.3 V supply voltage.

Keywords

VLSI; asynchronous transfer mode; bit-slice computers; multiplexing equipment; multistage interconnection networks; packet switching; protocols; telecommunication network routing; MOSIS; OC-12 link rate; VLSI implementation; bit-slice architecture; buffering scheme; delay sensitive ATM cells; input-output pair; mixed ATM/IP traffic; multiple paths; noninterleaving routing scheme; priority structure; routing stages; switch fabric; Asynchronous transfer mode; Delay; Fabrics; Routing; Switches; Switching systems; Testing; Traffic control; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific

Conference_Location

Yokohama, Japan

Print_ISBN

0-7803-5973-9

Type

conf

DOI

10.1109/ASPDAC.2000.835051

Filename

835051