A fractional-sampling-rate ADC-based CDR with feedforward architecture in 65nm CMOS

This paper presents a fractional-sampling-rate (FSR) CDR that blindly samples the received signal with an ADC at 1.45x the data rate and estimates the data phase using a feedforward architecture for clock and data recovery. The presented architecture reduces the ADC power by 27.3% compared to a 2x CDR. Measurements confirm that the FSR CDR recovers data with BER<10¹³ at 6.875 Gb/s from samples taken at 10 GS/S. The test-chip, implemented in 65 nm CMOS, occupies 0.3683 mm², and consumes 175.2 mW.