• DocumentCode
    1888793
  • Title

    A 16Gb/s 1st-Tap FFE and 3-Tap DFE in 90nm CMOS

  • Author

    Sugita, H. ; Sunaga, Keita ; Yamaguchi, Kazuhiro ; Mizuno, M.

  • Author_Institution
    NEC, Sagamihara, Japan
  • fYear
    2010
  • fDate
    7-11 Feb. 2010
  • Firstpage
    162
  • Lastpage
    163
  • Abstract
    A 16 Gb/s 1st-tap FFE and 3-tap DFE is developed featuring 33% faster operation than conventional DFEs. The presented technique is employed for high-speed 1st-tap ISI equalization and for jitter reduction in equalized edges. By-path feedback and a voltage swing limiter have been developed to speed-up both 2nd-tap and 3rd-tap equalization. The DFE is fabricated in a 90 nm CMOS process, occupies 227×276 ¿m2, and consumes 69 mW from a 1.4 V supply operating at a BER of <10-12 over a channel with 22 dB loss at 8 GHz.
  • Keywords
    CMOS integrated circuits; decision feedback equalisers; error statistics; 1st-tap FFE; 3-tap DFE; BER; CMOS process; ISI equalization; bit rate 16 Gbit/s; frequency 8 GHz; high-speed multitap decision feedback equalizer; jitter reduction; loss 22 dB; power 69 mW; size 90 nm; voltage 1.4 V; voltage swing limiter; Circuit noise; Clocks; Decision feedback equalizers; Delay; Intersymbol interference; Jitter; Noise cancellation; Output feedback; Sampling methods; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    0193-6530
  • Print_ISBN
    978-1-4244-6033-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2010.5434005
  • Filename
    5434005
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1888793