Title :
An algorithm for VLSI implementation of highly efficient cubic-polynomial evaluation
Author :
Mo, Fan ; Zhang, Yihua ; Yu, Jun ; Zhang, Qianling
Author_Institution :
ASIC, Fudan Univ., Shanghai, China
Abstract :
In this paper, we present a novel cubic-polynomial evaluation algorithm. It is suitable for VLSI implementation and the computational cost is reduced to about 66% of the previously reported method.
Keywords :
VLSI; application specific integrated circuits; iterative methods; polynomials; systolic arrays; VLSI implementation; computational cost; cubic-polynomial evaluation; iterative methods; systolic arrays; Analog-digital conversion; Application specific integrated circuits; Computational efficiency; Instruments; Iterative algorithms; Iterative methods; Performance evaluation; Polynomials; Systolic arrays; Very large scale integration;
Conference_Titel :
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location :
Yokohama, Japan
Print_ISBN :
0-7803-5973-9
DOI :
10.1109/ASPDAC.2000.835055
