DocumentCode
1888823
Title
Design of self-timed asynchronous Booth´s multiplier
Author
Tang, Tin-yau ; Choy, Chiu-Sing ; Siu, Pui-Lam ; Chan, Cheong-Fat
Author_Institution
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
fYear
2000
fDate
9-9 June 2000
Firstpage
15
Lastpage
16
Abstract
This paper presents a design of multiplier for the multiplication of two 8-bit two-complement numbers. The multiplier applies the self-timed asynchronous methodology such that the multiplier can be assumed to operate on average case delay. Also, modified Booth´s algorithm is used to reduce the number of partial products generated. As a result, the speed of the multiplier can be improved.
Keywords
asynchronous circuits; digital arithmetic; integrated circuit design; multiplying circuits; 8 bit; average case delay; multiplier speed; partial products; self-timed asynchronous Booth´s multiplier; two-complement numbers; Circuits; Clocks; Control systems; Decoding; Delay; Design methodology; Encoding; Energy consumption; Signal generators; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location
Yokohama, Japan
Print_ISBN
0-7803-5973-9
Type
conf
DOI
10.1109/ASPDAC.2000.835056
Filename
835056
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