DocumentCode
1888863
Title
A smart imager for the vision processing front-end
Author
Takeda, Noriaki ; Homma, Mituru ; Nagata, Makoto ; Morie, Takashi ; Iwata, Atsushi
Author_Institution
Adv. Sci. of Matter, Hiroshima Univ., Japan
fYear
2000
fDate
9-9 June 2000
Firstpage
19
Lastpage
20
Abstract
A CMOS PWM imager which realizes block summation and 2D projection of a thresholded image, in addition to row-parallel PWM readout with gray scale, is reported. An imager including 56/spl times/56 pixels, an address signal generator, and a signal processing circuit is fabricated in a 6 mm/spl times/6 mm chip with a 0.8 /spl mu/m CMOS technology.
Keywords
CMOS image sensors; computer vision; intelligent sensors; pulse width modulation; 0.8 micron; 2D projection; 3136 pixel; 56 pixel; CMOS PWM imager; address signal generator; block summation; gray scale; row-parallel PWM readout; signal processing circuit; smart imager; thresholded image; vision processing front-end; CMOS image sensors; CMOS process; CMOS technology; Capacitors; Pulse generation; Pulse width modulation; Signal generators; Signal processing; Space vector pulse width modulation; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2000. Proceedings of the ASP-DAC 2000. Asia and South Pacific
Conference_Location
Yokohama, Japan
Print_ISBN
0-7803-5973-9
Type
conf
DOI
10.1109/ASPDAC.2000.835058
Filename
835058
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